The present invention relates to a signal-processing circuit having a field-effect transistor and a bipolar transistor connected in cascade to the field-effect transistor.
A gain-controlled amplifier for use in a high-frequency amplifying stage, such as a tuner, has the structure shown in FIG. 1 or that shown in FIG. 4.
The amplifier of FIG. 1 is disclosed in Japanese Patent Disclosure Sho No. 61-160170. This circuit comprises a MOSFET 11 (metal oxide semiconductor field-effect transistor) used as the first stage, and another MOSFET 12 used as the second stage and cascade-connected to MOSFET 11. The gate of FET 11 is connected to input terminal 1 which in turn is coupled to an input tuning circuit (not shown), and can receive a DC bias signal and an input signal from the tuning circuit via input terminal 1. A predetermined voltage (usually, the ground potential) is applied to the gate of FET 12 through gain control terminal 3. The drain of FET 12 is connected to output terminal 4.
The amplifier shown in FIG. 4 is disclosed in Integrated Electronics, McGraw-Hill, Inc., pp 566-569. This circuit comprises an NPN transistor 13 used as the first stage, and an NPN transistor 14 used as the second state and which is cascade-connected to NPN transistor 13. The base of transistor 13 is coupled to input terminal 1. The emitter of transistor 13 is connected to terminal 2 held at a predetermined potential. The base and collector of transistor 14 are connected to gain control terminal 3 and output terminal 4, respectively.
The amplifier of FIG. 1 amplifies the signal supplied to input terminal 1 when a predetermined operation current flows through first-stage FET 11 and second-stage FET 12. The amplifier has one drawback, however. Its input-output characteristic contains prominent third distortion components. This is because the MOSFETs have a high equivalent resistance, due to their structure and function. More specifically, the amplifier exhibits the DC input-output characteristics shown in FIG. 2, when a gain control voltage is applied to the gate of FET 12. The DC input-output characteristic is the relation between voltage V12 between terminals 1 and 2, and current I42 flowing between terminals 2 and 4. In FIG. 2, voltage V32 between terminals 2 and 3 (i.e., the gain-controlling voltage) is regarded as a parameter, and voltage V42 between terminals 2 and 4 is fixed at 6 V. The equivalent resistance of FETs 11 and 12 affects the prominence of the third distortion components of output current I42 near the boundary between the region where the characteristic of FET 11 is predominant and current I42 is thus small, and the region where the characteristic of FET 12 is predominant and current I42 is large. By differentiating the input-output characteristic curve shown in FIG. 2, we can obtain the forward transmission admittance .vertline.Yf.vertline. (=.DELTA.I42/.DELTA.V12) with respect to input voltage V12, which is shown in FIG. 3. The inflection points shown in FIG. 3 correspond to the third distortion components of the input-output characteristic curve (FIG. 2). As FIG. 3 clearly shows, there are inflection points where the slope of the characteristic curve is steep. This means that the characteristic curve has prominent third distortion components. FIG. 3 further reveals that there are two inflection points where gain-controlling voltage V32 falls. If such is the case, the third distortion components will become more prominent.
In the amplifier shown in FIG. 4, the equivalent resistance of the collector-emitter path of transistor 13 is far lower than that of either MOSFET used in the amplifier of FIG. 1. However, the input-output characteristic curve of the amplifier shown in FIG. 4 also has prominent third distortion components. This is inevitably because the first-stage transistor is a bipolar transistor.